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ics for consumer electronics single chip pip system sda 9288x (a141) pip 2 data sheet 03.96
edition 03.96 this edition was realized using the software system framemaker a . published by siemens ag, bereich halbleiter, marketing- kommunikation, balanstra?e 73, 81541 mnchen ? siemens ag 1996. all rights reserved. attention please! as far as patents or other rights of third par- ties are concerned, liability is only assumed for components, not for applications, pro- cesses and circuits implemented within com- ponents or assemblies. the information describes the type of compo- nent and shall not be considered as assured characteristics. terms of delivery and rights to change design reserved. for questions on technology, delivery and prices please contact the semiconductor group offices in germany or the siemens companies and representatives worldwide (see address list). due to technical requirements components may contain dangerous substances. for in- formation on the types in question please contact your nearest siemens office, semi- conductor group. siemens ag is an approved cecc manufac- turer. packing please use the recycling operators known to you. we can also help you C get in touch with your nearest sales office. by agreement we will take packing material back, if it is sorted. you must bear the costs of transport. for packing material that is returned to us un- sorted or which we are not obliged to accept, we shall have to invoice you for any costs in- curred. components used in life-support devices or systems must be expressly authorized for such purpose! critical components 1 of the semiconductor group of siemens ag, may only be used in life-support devices or systems 2 with the ex- press written approval of the semiconductor group of siemens ag. 1 a critical component is a component used in a life-support device or system whose failure can reasonably be expected to cause the failure of that life-support de- vice or system, or to affect its safety or ef- fectiveness of that device or system. 2 life support devices or systems are in- tended (a) to be implanted in the human body, or (b) to support and/or maintain and sustain human life. if they fail, it is reasonable to assume that the health of the user may be endangered.
sda 9288x revision history: current version: 03.96 previous version: page (in previous version) page (in new version) subjects (major changes since last revision) 25.1.1994: preliminary specification v1.1 22; 23; 24 25.1.1994: warnings 24 25.1.1994: additional bits vsiisq, vspisq at subad. 07/08 25 25.1.1994: additional bits daconde, daconst at subad. 0d 26 25.1.1994: supply voltage range 32 25.1.1994: values dac 35 25.1.1994: diagram 43 25.1.1994: influence hsidel to vsidel adjustment 19; 21 19.4.1994: additional note pll switch read27 43 19.4.1994: timing of adc clamping 15 20.6.1994: warning subaddr. 02 20; 25 20.6.1994: additional bit seldown at subaddr. 0b 23 20.6.1994: value v ol outputs sel, seld added all 18.7.1994: pages no. shifted 10; 15; 18 18.7.1994: improvement: additional bits d5, d6 (clps; clpfix) at subaddr. 06 15; 19 18.7.1994: bit d0 of subaddress 0d deleted 17 18.7.1994: new: examples for adjustment of frame colors 17 18.7.1994: text bits imod, pmod 22 18.7.1994: additional remark at subaddress 02 25 18.7.1994: clamping current. additional values 28; 29 18.7.1994: application board layout and application circuit new 30 18.7.1994: timing of adc clamping changed 32 18.7.1994: values dac output current
sda 9288x table of contents page semiconductor group 4 03.96 1 general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 1.2 pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 1.3 pin definitions and functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 1.4 functional block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2 system description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.1 ad conversion, inset synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.2 input signal processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.3 pip field memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.4 output signal processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2.4.1 matrix equations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2.4.2 frame insertion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2.4.3 select signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2.5 da conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 2.6 pll . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 2.7 i 2 c bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 2.7.1 i 2 c bus addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 2.7.2 i 2 c bus receiver format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 2.7.3 i 2 c bus commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 3.1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 3.2 operational range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 3.3 characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 4 diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 4.1 output current of da converters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 4.2 application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 4.2.1 reference voltage generation for adc . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 4.2.2 adjustment of ydel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 4.2.3 three level interface (3-l) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 4.2.4 application board layout proposal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 4.2.5 application circuit (r, g, b-mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 4.3 waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 4.3.1 timing of adc clamping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 4.3.2 phase relation of sync pulses at frame mode . . . . . . . . . . . . . . . . . . . . . . 43 5 package outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 i 2 c bus purchase of siemens i 2 c components conveys the license under the philips i 2 c patent to use the components in the i 2 c system provided the system conforms to the i 2 c specifications defined by philips.
sda 9288x semiconductor group 5 03.96 1 general description the picture-in-picture processor sda 9288x a141 generates a picture of reduced size of a video signal (inset channel) for the purpose of combining it with another video signal (parent channel). the easy implementation of the ic in an existing system needs only a few additional external components. there is a great variety of application facilities in professional and consumer products (tv sets, supervising monitors, multi-media, )
p-dso-32-2 semiconductor group 6 03.96 single chip pip system sda 9288x data sheet mos type ordering code package sda 9288x on request p-dso-32-2 212 luminance and 53 chrominance pixels per inset line for picture size 1/9 6-bit amplitude resolution for each incoming signal component field and frame mode display horizontal and vertical filtering special antialias filtering for the luminance signal ? 16:9 compatibility operation in 4:3 and 16:9 sets 4:3 inset signals on 16:9 displays or v.v. with picture size 1/9 and 1/16, respectively ? analog inputs y, + (b-y), + (r-y) or y, -(b-y), -(r-y) ? analog outputs y, + (b-y), + (r-y) or y, C (b-y), C (r-y) or rgb 3 rgb matrices: ebu, ntsc (japan), ntsc (usa) ? free programmable position of inset picture steps of 1 pixel and 1 line all pip and pop positions are possible ? programmable framing 4096 frame colors variable frame width 1.1 features ? single chip solution clamping, ad conversion, filtering, field memory, rgb matrix, da-conversion and clock generation integrated on one chip ? 2 picture sizes 1/9 or 1/16 of normal size ? high resolution display 13.5 mhz/27 mhz display clock frequency
sda 9288x semiconductor group 7 03.96 ? freeze picture ? i 2 c bus control ? threefold pip/pop facility three different i 2 c-addresses (pin-programmable) tri-state outputs ? numerical pll circuit for high stability clock generation ? no necessity of pal/secam delay lines (using suitable color decoders i.e. tda 8310) ? multistandard applications 625 lines/525 lines standard (inset and parent channel) scan conversion systems as flickerfree display systems (parent channel) hdtv (parent channel) ? p-dso-32-2 package/350 mil (smd) ? 5 v supply voltage
sda 9288x semiconductor group 8 03.96 1.2 pin configuration (top view) figure 1 p-dso-32-2
sda 9288x semiconductor group 9 03.96 1.3 pin definitions and functions pin no. symbol function 1) descriptions 1 v ssa1 s analog voltage supply ( v ss ) for adc 2 v refl i lower reference voltage for ad converters 3 xin i quartz oscillator (input) or quartz clock (from another pip ic) or line locked clock (27 mhz, from a digital parent channel) 4 xq q quartz oscillator (output) 5 v dd s digital voltage supply ( v dd ) 6 v ssa2 s analog voltage supply ( v ss ) for dac and pll 7 out1 q/ana analog output: chrominance signal + (r-y) or C (r-y) or r 8 out2 q/ana analog output: luminance signal y or g 9 out3 q/ana analog output: chrominance signal + (b-y) or C (b-y) or b 10 v dda2 s analog voltage supply ( v dd ) for dac and pll 11 i ref q/ana reference current for da-converters 12 sel q single frequency fast pip switching output (tristate) 13 seld q double frequency fast pip switching output (tristate) 14 v bb s capacitor connection for smoothing internally generated substrate bias 15 adr i 3-l i 2 c bus address control 16,27 v ss s digital voltage supply ( v ss ) 17 vp i multifrequency vertical sync for parent channel 18 hp/scp i multifrequency horizontal sync for parent channel 19 vpd/vi i double frequency vertical sync for parent channel or vertical sync input for inset channel 20 hpd/sci i double frequency horizontal sync for parent channel or horizontal sync input for inset channel 21 sda i/q i 2 c bus data 22 scl i i 2 c bus clock 23 sw1 q 3-l i 2 c bus controlled output1 24 sw2 q 3-l i 2 c bus controlled output2 1) i : input, q : output, ana : analog, ttl : digital (ttl), 3-l : 3-level, s : supply voltage
sda 9288x semiconductor group 10 03.96 25 hvi i 3-l special 3-level hor. and vert. sync signal for inset channel 26 sys i 3-l input for standard depending internal switching (low (l) = pal, mid (m) = ntsc, high (h) = secam) 28 yin i/ana analog input: luminance signal y 29 vdda1 s analog voltage supply ( v dd ) for adc 30 uin i/ana analog input: chrominance signal + (b-y) or C (b-y) 31 vrefh i upper reference voltage for ad converters 32 vin i/ana analog input: chrominance signal + (r-y) or C (r-y) i : input, q : output, ana : analog, ttl : digital (ttl), 3-l : 3-level, s : supply voltage 1.3 pin definitions and functions (contd) pin no. symbol function 1) descriptions
sda 9288x semiconductor group 11 03.96 1.4 functional block diagram figure 2
sda 9288x semiconductor group 12 03.96 2 system description 2.1 ad conversion, inset synchronization the inset video signal is fed to the sda 9288x a141 as analog luminance and chrominance components 1) . the polarity of the chrominance signals is programmable. after clamping the video components are ad-converted with an amplitude resolution of 6 bit. the conversion is done using a 13.5 mhz clock for the luminance signal and a 3.375 mhz clock for the chrominance signals. for the adaption to different application the clamp timing for the analog inputs can be chosen (clps; clpfix). setting this bits to 1 can be useful for non-standard input signals. for inset synchronization it is possible to feed either a special 3-level signal via pin hvi (detection of horizontal and vertical pulses) or separate signals via pins sci for horizontal and vi for vertical synchronization. sci is the horizontal synchron signal of the inset channel. if the burst gate pulse of the sandcastle is used it must be adapted to ttl compatible levels by a simple external circuit. centering of the displayed picture area is possible by a programmable delay for the horizontal synchronization signal (hsidel). the inset horizontal synchronization signals are sampled with 27 mhz. this 27 mhz clock and the ad converter clocks are derived from the parent horizontal synchronization pulse (see chapter 2.6 ) or from the quartz frequency converted by a factor of 4/3. delay differences between luminance and chrominance signals at the input of the ic caused by chroma decoding are compensated by a programmable luminance delay line (ydel) of about C 290 ns 740 ns (at decimation input; see application information ). by analyzing the synchronization pulses the line standard of the inset signal source is detected and interference noise on the vertical sync signal is removed. for applications with fixed line standard (only 625 lines or 525 lines) the automatic detection can be switched off. the phase of the vertical sync pulse is programmable (vsidel; vspdel). by this way a correct detection of the field number is possible, an important condition for frame mode display. note: the adjustment of vsidel is influenced by hsidel (see chapter 4.3 ), vertical synchronization via pin hvi causes an additional internal delay for the vertical sync pulse of about 16 m s. 1) to improve the signal-to-noise ratio the amplitude of the input signals should be as large as possible.
sda 9288x semiconductor group 13 03.96 2.2 input signal processing this stage performs the decimation of the inset signal by horizontal and vertical filtering and sub-sampling. a special antialias filter improves the frequency response of the luminance channel. it is optimized for the use of the horizontal decimation factor 3:1. a window signal, derived from the sync pulses and the detected line standard, defines the part of the active video area used for decimation. for hsidel = 0 the decimation window is opened about 104 clock periods (13.5 mhz) after the horizontal synchronization pulse. for the 625 lines standard the 36th video line is the first decimated line, for the 525 lines standard decimation starts in the 26th video line. the following filters are implemented: the realized chrominance filtering allows omitting the color decoder delay line for pal and secam demodulation if the color decoder supplies the same output voltages independent of the kind of operation. in case of secam signals an amplification of the chrominance signals by a factor of 2 is necessary because just every second line a signal is present. this chrominance amplification is programmable via pin sys or i 2 c bus (amsec). the horizontal and vertical decimation factors are free programmable (dechor, decver). using different decimations horizontal and vertical 16:9 applications become realizable: dechor = 1, decver = 0: picture size 1/9 for 4:3 inset signals on 16:9 displays dechor = 0, decver = 1: picture size 1/16 for 16:9 inset signals on 4:3 displays horizontal decimation component filter 3:1 luminance 1 + z C1 +z C2 3:1 chrominance 1 + 2 z C1 +z C2 4:1 luminance 1 + z C1 +z C2 +z C3 4:1 chrominance 1 + z C1 +z C2 +z C3 vertical decimation component filter 3:1 luminance 1 + z Cl +z C2l 3:1 chrominance 1 + 2 z Cl +z C2l 4:1 luminance 1 + z Cl +z C2l +z C3l 4:1 chrominance 1 + z Cl +z C2l +z C3l z = e j w t ,t = 1/13.5 mhz for luminance t = 1/3.375 mhz for chrominance l = samples per line for luminance respectively chrominance
sda 9288x semiconductor group 14 03.96 2.3 pip field memory the on-chip memory stores one decimated field of the inset picture. its capacity is 169 812 bits. the picture size depends on the horizontal and vertical decimation factors. in field mode display just every second inset field is written into the memory, in frame mode display the memory is continuously written. data are written with the lower inset clock frequency depending on the horizontal decimation factor (4.5 mhz or 3.375 mhz). normally the read frequency is 13.5 mhz and 27 mhz for scan conversion systems. for progressive scan conversion systems and hdtv displays a line doubling mode is available (linedbl). every line of the inset picture is read twice. memory writing can be stopped by program (freeze), a freeze picture display results (one field). having no scan conversion and the same line numbers in inset and parent channel (625 lines or 525 lines both) frame mode display is possible. the result is a higher vertical and time resolution because of displaying every incoming field. for this purpose the standards are internally analysed and activating of frame mode display is blocked automatically when the described restrictions are not fulfilled. as in the inset channel a field number detection is carried out for the parent channel. depending on the phase between inset and parent signals a correction of the display raster for the read out data is performed by omitting or inserting lines when the read address counter outruns the write address counter. the display position of the inset picture is free programmable (poshor, posver). the first possible picture position (without frame) is 54 clock periods (13.5 mhz or 27 mhz) after the horizontal and 4 lines after the vertical synchronization pulses. starting at this position the picture can be moved over the whole display area. even pop-positions (picture outside picture) at 16:9 applications are possible. horizontal decimation pip pixels per line y (b-y) (r-y) 3:1 212 53 53 4:1 160 40 40 vertical decimation line standard pip lines 3:1 625 88 3:1 525 76 4:1 625 66 4:1 525 57
sda 9288x semiconductor group 15 03.96 having different line standards in inset and parent channels we have a so called mixed mode display. it causes deformations in the aspect ratio of the inset picture. a special mixed mode display is available for the picture size 1/9 (mixdis): C parent channel 625 lines, inset channel 525 lines: the inset picture is shifted down by 6 lines. by performing this shifting the centers of the inset pictures have the same position for both line standards. C parent channel 525 lines, inset channel 625 lines: the inset picture gets a reduced line number of 76. the first and the last 6 lines are omitted. this way the inset picture size is the same as for 525 lines inset signals. the display shows the center part of the original picture. synchronization of memory reading with the parent channel is achieved by processing the parent horizontal and vertical synchronization signals in the same way as described for the inset channel. the synchronization signals are fed to the ic at pin hp/scp for horizontal synchronization and pin vp for vertical synchronization. in the same way as described for the inset channel the burst gate of the sandcastle signal can be used for horizontal synchronization. in scan conversion systems also the inputs hpd/sci and vpd/vi are available if the input hvi is activated for inset synchronization.
sda 9288x semiconductor group 16 03.96 2.4 output signal processing at the memory output the chrominance components are demultiplexed and linearly interpolated to the luminance sample rate. different output formats are available: luminance signal y with inverted or non-inverted chrominance signals (b-y), (r-y) or rgb. for the rgb conversion 3 matrices are integrated: matrix selection is done by pin sys or i 2 c bus. the matrices are designed for the following input voltages (100 % white, 75 % color saturation): standard b-y r-y g-y b-y r-y g-y ebu 1 0.558 0.345 0 90 237 ntsc (japan) 1 0.783 0.31 0 95 240 ntsc (usa) 1 1.013 0.305 0 104 252 component input voltage (without sync) in % of full scale input range of adc y75 b-y 100 r-y 100
sda 9288x semiconductor group 17 03.96 2.4.1 matrix equations ebu ntsc (japan) ntsc (usa) 2.4.2 frame insertion a colored frame is added to the inset picture. 4096 frame colors are programmable, 4 bits for each component y, (b-y), (r-y) (bits fry, fru, frv). the horizontal and r g b 101 0 0.78125 1 0.1875 C 0.40625 C 1 by C ry C y = r g b 101 0.0625 C 1.09375 1 0.15625 C 0.375 C 1 by C ry C y = r g b 101 0.25 C 1.375 1 0.09375 C 0.40625 C 1 by C ry C y =
sda 9288x semiconductor group 18 03.96 vertical width of the frame are independently programmable. width = 0 means display without frame. examples for the adjustment of frame colors 2.4.3 select signal for controlling an external switch (for example an rgb processor) a select signal is supplied. pin sel is active in normal 13.5 mhz reading mode, pin seld is active using 27 mhz. the phases of these signals are programmable for adaption to different external output signal processing. frame color fry d3 d0 of subaddress 09 fru d3 d0 of subaddress 0a frv d7 d4 of subaddress 0a blue 0100 0110 1010 green 0100 1000 1010 white 1100 0000 0000 red 0100 1000 0111 yellow 1100 1000 0100 cyan 1100 0010 1010 magenta 0100 0110 0100
sda 9288x semiconductor group 19 03.96 2.5 da conversion the sda 9288x a141 includes three 6-bit da converters. each converter supplies a current through an external resistor that is connected between v ssa and out1, out2, out3 respectively. the current is controlled by a digital control circuit. each command daconst or pipon starts the adjustment cycle. 2.6 pll a numerical pll circuit supplies a clock of about 27 mhz with high stability. the generated clock is locked to the parent horizontal synchronization pulse. its frequency depends linearly on the frequency of the sync signal and the quartz frequency. the recommended quartz frequencies are listed under recommended operation conditions. using up to three sda 9288x a141 ics in one application only a single quartz is necessary. four time constants are programmable via i 2 c bus. if the pll is switched off an external 27 mhz parent line locked clock can be fed to the ic. the inset clock generation is possible in two ways: 1. synchron with the parent horizontal synchronization pulse (bit clisw = 0) 2. synchron with the quartz frequency (bit clisw = 1; f cli = 4/3 f quartz ). in this mode the aspect ratio is independent on the parent sync frequency but depends on the used resonator type. it is only possible to use one of the two modes. note: before setting bit d3 of subaddress 00 (read27) noise reduction of the vsp pulse must be switched off (d5 of subaddress 08 = 1). 2.7 i 2 c bus 2.7.1 i 2 c bus addresses three different i 2 c addresses are programmable via pin adr. 2.7.2 i 2 c bus receiver format s: start condition a: acknowledge p: stop condition only write operation is possible. an automatically address increment function is implemented. pin adr address (bin.) address (hex.) low level ( v ss or v ssa ) 11010110 d6 mid level (open) 11011100 dc high level ( v dd or v dda ) 11011110 de s address a subaddress a data byte a **** a p
sda 9288x semiconductor group 20 03.96 2.7.3 i 2 c bus commands after switching on the ic the data bytes of all registers are set to 0, the bit plloff is set to 1. sub- addr. data bytes hex d7 d6 d5 d4 d3 d2 d1 d0 00 0 sysact freeze plloff read27 linedbl frame pipon 01 0 seldel3 seldel2 seldel1 seldel0 mixdis poshor9 poshor8 02 poshor7 poshor6 poshor5 poshor4 poshor3 poshor2 poshor1 poshor0 03 posver7 posver6 posver5 posver4 posver3 posver2 posver1 posver0 04 0 sw21 sw20 sw11 sw10 ydel2 ydel1 ydel0 05 decver dechor inshvi chrins pmod1 pmod0 imod1 imod0 06 0 clps clpfix clisw hsidel3 hsidel2 hsidel1 hsidel0 07 amsec 0 vsiisq vsidel4 vsidel3 vsidel2 vsidel1 vsidel0 08 parsynd 0 vspisq vspdel4 vspdel3 vspdel2 vspdel1 vspdel0 09 con3 con2 con1 con0 fry5 fry4 fry3 fry2 0a frv5 frv4 frv3 frv2 fru5 fru4 fru3 fru2 0b 0 0 seldown frwidv1 frwidv0 frwidh2 frwidh1 frwidh0 0c 0 0 0 mat2 mat1 mat0 chrpip outfor 0d daconst plltc1 plltc2 0 0 0 0 0
sda 9288x semiconductor group 21 03.96 bit name function subaddress 00 d0 pipon 0: pip insertion off 1: pip insertion on d1 frame 0: field display 1: frame display (under special restrictions). correct adjustment of bits vsidel, vspdel required (see chapter 4.3 ) d2 linedbl 0: each line of the pip memory is read once (normal operation) 1: each line of the pip memory is read twice (line doubling for progressive scan conversion systems in parent channel) d3 read27 0: pip display with single read frequency (13.5 mhz) 1: pip display with double read frequency (27 mhz) (see note page 19 ). d4 plloff 0: internal pll on 1: internal pll off (external clock generation) d5 freeze 0: live picture 1: freeze picture d6 sysact 0: pin sys inactive: selection of decimation amplification and rgb-matrix is done via i 2 c bus 1: pin sys active: selection of decimation amplification and rgb-matrix is done via pin sys subaddress 01 d1 d0 poshor 2 msbs of poshor (see also subaddress 02) d2 mixdis 0: pip picture height depends just upon inset line standard, position upon poshor 1: modified pip picture height and position for different inset and parent line standards (mixed display mode) d6 d3 seldel delay of output signal select at pins sel respectively seld (C87 periods of read frequency clock, programmable in 2s complement code). seldel = 0: select signal has the same phase as the pip picture signal referenced to the ic output.
sda 9288x semiconductor group 22 03.96 subaddress 02 d7 d0 poshor horizontal position of pip picture (raster: 1 pixel) note: the 2 msbs of poshor are located at subaddress 01 warning: it is not allowed to adjust positions < 2 and > 740. note: to avoid horizontal jumping of the picture by changing poshor from 00 1111 1111 to 01 0000 0000 its necessary to transfer the bits of both subaddresses during the same field period. subaddress 03 d7 d0 posver vertical position of pip picture (raster: 1 line) warning: it is not allowed to adjust positions > 220 (50 hz) or > 182 (60 hz). subaddress 04 d2 d0 ydel delay of luminance input signal 000: minimum delay 111: maximum delay; see chapter 4.2 d4 d3 sw1 direct control of output pin sw1 (3 levels) 00: low level 01: mid level 10: high level 11: high level d6 d5 sw2 direct control of output pin sw2 (3 levels) 00: low level 01: mid level 10: high level 11: high level bit name function
sda 9288x semiconductor group 23 03.96 subaddress 05 d1 d0 imod 00: automatic detection of line standard (inset signal) 01: fixed adjustment 625 lines 1) 10: fixed adjustment 525 lines 1) 11: freeze last line standard d3 d2 pmod 00: automatic detection of line standard (parent signal) 01: fixed adjustment 625 lines 1) 10: fixed adjustment 525 lines 1) 11: freeze last line standard d4 chrins 0: chrominance input signals + (b-y), + (r-y) 1: inverted chrominance input signals C (b-y), C (r-y) d5 inshvi 0: inset synchronization signals via pins hpd/sci and vpd/vi 1: inset synchr. signals via pin hvi (3-i. sand-castle signal) d6 dechor 0: horizontal decimation 3 to 1 1: horizontal decimation 4 to 1 d7 decver 0: vertical decimation 3 to 1 1: vertical decimation 4 to 1 subaddress 06 d3 d0 hsidel delay of horizontal synchronization pulse (inset signal) raster: 6 clock periods of 13.5 mhz. warning: adjustment of hsidel will influence the adjustment of vsidel (subaddr. 07); see chapter 4.3 d4 clisw 0: inset clock synchronized with parent clock 1: inset clock synchronized with quartz frequency note: only one of the two modes can be used. switching back from 1 to 0 is not possible! d5 clpfix 0: clamp pulses of adc are dependent on the adjustment of hsidel 1: clamp pulses fixed; no influence of hsidel d6 clps 0: three clamp cycles per line (timing see diagram) 1: two clamp cycles per line 1) fixed adjustments for imod and pmod result in undefined working conditions when signal standards are used which are different from the programmed values. bit name function
sda 9288x semiconductor group 24 03.96 subaddress 07 d4 d0 vsidel delay of vertical synchronization pulse (inset signal) in steps of 2.37 m s. warning: correct adjustment value is influenced by the adjustment of hsidel (subaddr. 06); see chapter 4.3 . d5 vsiisq noise reduction of the vsi pulse (set to 0 under normal conditions) d7 amsec 0: unity amplification of decimation filters (normal mode) 1: amplification by a factor of 2 (secam signals without delay line in the chroma decoder) subaddress 08 d4 d0 vspdel delay of vertical synchronization pulse (parent signal) in steps of 2.37 m s/1.68 s (50/100 hz) d5 vspisq noise reduction of the vsp pulse (should be set to 0 under normal conditions); in case changing from standard mode to line or frame conversion modes 1 should be set during the changement of line frequency d7 parsynd 0: parent synchronization signals for double frequency read via pins hp/scp and vp 1: parent synchronization signals for double frequency read via pins hpd/sci and vpd/vi (inshvi = 1 required) subaddress 09 d3 d0 fry luminance component of frame color (4 msbs of 6 bit) d7 d4 con contrast adjustment of pip picture; steps and adjustment range depending on the external output resistors. proposed value see chapter 3.3 subaddress 0a d3 d0 fru chrominance component (b-y) of frame color (4 msbs of 6 bit) d7 d4 frv chrominance component (r-y) of frame color (4 msbs of 6 bit) bit name function
sda 9288x semiconductor group 25 03.96 subaddress 0b d2 d0 frwidh horizontal width of pip frame (0 7 pixels) d4 d3 frwidv vertical width of pip frame (0 3 lines) d5 seldown 0: open source output at pins sel, seld 1: ttl output at pins sel, seld subaddress 0c d0 outfor 0: format of output signals: y, (b-y), (r-y) 1: format of output signals: r g b d1 chrpip 0: chrominance output signals: + (b-y), + (r-y) 1: inverted chrominance output signals: C (b-y), C (r-y) d2 mat0 0: ebu rgb-matrix 1: ntsc rgb-matrix d3 mat1 0: preselection of ntsc rgb matrix (usa) 1: preselection of ntsc rbg matrix (japan) d4 mat2 0: matrix selection by bit mat0 1: automatic matrix selection depending on inset line standard subaddress 0d d0 daconde set to 0 d5 plltc2 time constant of internal pll: 00: medium damping, low resonance frequency 01: medium damping, high resonance frequency d6 plltc1 10: high damping, low resonance frequency 11: high damping, high resonance frequency note: after power on plltc must remain at 00 until the system is locked. d7 daconst changing from 0 to 1 starts automatic adjustment of out1 3 output current (switching pipon gives the same result). bit name function
sda 9288x semiconductor group 26 03.96 note: all voltages listed are referenced to ground (0 v, v ss ) except where noted. stresses above those listed here may cause permanent damage to the device. exposure to absolute maximum rating conditions for extended periods may affect device reliability. 3 electrical characteristics 3.1 absolute maximum ratings parameter symbol limit values unit remark min. max. ambient temperature t a 070 c storage temperature t stg C 55 125 c junction temperature t j 125 c soldering temperature t sold 260 c duration < 10 s input voltage v i C 0.5 v v dd + 0.5 v 1 analog inputs (yin, uin, vin, i ref ) v i C 1 7 v all other pins output voltage v q C 0.5 v v dd + 0.5 v 1 pins out1, out2, out3, xq, sw1, sw2 v q C 1 7 v all other pins supply voltages v dd C1 7 v supply voltage differentials v dd d C 0.25 0.25 v total power dissipation p tot 900 mw latch-up protection C 100 100 ma except pins out1, out2, out3, i ref , xq, xq, yin, uin, vin
sda 9288x semiconductor group 27 03.96 3.2 operational range parameter symbol limit values unit remark min. typ. max. supply voltages v ddxx 4.75 5 5.5 v ambient temperature t a 02570 c all ttl inputs low-level input voltage v il C 1 0.8 v high-level input voltage v ih 2.0 6 v all three level inputs (3-l) (see figure) high-level input voltage v ih 3.5 6 v low-level input voltage v il C 1 0.8 v medium-level voltage v im open input, see chapter 3.3 all 3-l outputs (see figure) high-level output current i oh C 500 0 m a low-level output current i ol 0 1.6 ma inset horizontal sync ttl and 3-l inputs: hpd/sci, hvi 1) horizontal frequency 14.53 16.72 khz signal rise time 100 ns noisefree l/m-to-h transition signal high time 100 ns signal medium or low time 900 ns 1) all values are referred to the corresponding min ( v ih ), max ( v im ) and max ( v il )
sda 9288x semiconductor group 28 03.96 inset vertical sync ttl and 3-l inputs: vpd/vi, hvi 1) signal medium or high time 17 m s necessary for vertical sync detection signal low time 200 ns parent horizontal sync ttl inputs: hp/scp, hpd/sci 2) sync frequency in single frequency display mode 14.53 16.72 khz quartz frequency 20.480 mhz 15 17.19 khz quartz frequency 21.090 mhz sync frequency in double frequency display mode 29.06 33.44 khz quartz frequency 20.480 mhz 30 34.375 khz quartz frequency 21.090 mhz signal rise time 100 ns noisefree transition signal high time 100 ns signal low time 900 ns parent vertical sync ttl input vdp/vi 2) signal high time 200 ns signal low time 200 ns 1) all values are referred to the corresponding min ( v ih ), max ( v im ) and max ( v il ) 2) all values are referred to the corresponding min ( v ih ) and max ( v il ) 3.2 operational range (contd) parameter symbol limit values unit remark min. typ. max.
sda 9288x semiconductor group 29 03.96 quartz/ceramic resonator 2) recommended frequency 20.25 20.48 21.3 mhz 21.09 mhz for muse series resistance 10 w c 1 , c 2 33 pf 20 w c 1 , c 2 22 pf 30 w c 1 , c 2 15 pf 40 w c 1 , c 2 10 pf (total series capacitance) optional ttl clock input: xin 1) clock input cycle time 35 40 ns external line locked; 27 mhz clock ( i 2 c: internal pll off) clock input rise time 5 ns clock input fall time 5 ns clock input low time 10 ns clock input high time 10 ns fast i 2 c bus 1) 3) scl clock frequency f scl 0 400 khz inactive time before start of transmission t buf 1.3 m s setup time start condition t su; sta 0.6 m s hold time start condition t hd; sta 0.6 m s scl low time t low 1.3 m s 1) all values are referred to min ( v ih ) and max ( v il ). 2) there is no internal protection for the crystal driver against oscillation at harmonic frequencies. 3) this specification of the bus lines does not have to be identical with the i/o stages specification because of optional series resistors between bus lines and i/o pins. 3.2 operational range (contd) parameter symbol limit values unit remark min. typ. max.
sda 9288x semiconductor group 30 03.96 scl high time t high 0.6 m s setup time data t su; dat 100 ns hold time data t hd;dat 0 0.9 m s sda/scl rise/fall times t r , t f 20 + $ 300 ns $ = 0.1 c b /pf setup time stop condition t su; sto 0.6 m s capacitive load/bus line c b 400 pf i 2 c bus inputs/output: sda, scl high-level input voltage v ih 3 v dd + 0.5 v also for sda/scl input stages low-level input voltage v il C 0.5 1.5 v spike duration at inputs 0050ns low-level output current i ol 6ma analog to digital converters (6 bit) input coupling capacitors 10 100 nf necessary for proper clamping y, u, v source resistance 1k w reference voltage low v refl 0.5 1.0 1.5 v min and max values only with optional external resistors, see also chapter 3.3 . reference voltage high v refh 1.5 2.0 2.5 v reference voltage difference v refh C v refl 0.5 1.0 2 v 3.2 operational range (contd) parameter symbol limit values unit remark min. typ. max.
sda 9288x semiconductor group 31 03.96 note: in the operational range the functions given in the circuit description are fulfilled. digital-to-analog converters (6 bit) full range output voltage v ofr 1 2 v peak to peak reference resistance r ref1 4.2 5.1 6.3 k w bits con = 0000; no contrast adjustment used r ref2 6.0 6.8 7.5 k w contrast adjustment via i 2 c bus 3.2 operational range (contd) parameter symbol limit values unit remark min. typ. max.
sda 9288x semiconductor group 32 03.96 3.3 characteristics parameter symbol limit values unit remark min. max. average total supply current i ddtot 160 ma i ddtot = i dd + i dda1 + i dda2 note: the maxima do not necessarily coincide. average digital supply current i dd 120 ma average analog supply current i dda1 40 ma average analog supply current i dda2 20 ma all digital inputs (ttl, i 2 c) input capacitance c i 7 pf not tested input leakage current C 10 10 m a including leakage current of sda output stage all three level inputs (3-l) (see figure) input capacitance c i 7 pf not tested medium-level open input voltage v im 2.1 2.5 v | i in | 1 m a , v dd = 5 v differential input resistance r in 814k w not tested sel, seld high-level output voltage v oh 2.4 v v dd v i oh = C 200 m a high-level output voltage v oh 1.5 v v dd v i oh = C 4.5 ma low-level output voltage v ol 0.4 v i ol = 1.6 ma, only valid if bit seldown = 1 leakage current C 10 a v o =0v v dd output capacitance 7 pf not tested all 3-l outputs high-level output voltage v oh 4v i oh = C 100 m a high-level output voltage v oh 3.9 v i oh = C 500 m a low-level output voltage v ol 0.4 v i ol = max
sda 9288x semiconductor group 33 03.96 medium-level output leakage current i om C1 1 m a tristate output capacitance 7 pf not tested i 2 c inputs: sda/scl schmitt trigger hysteresis v hys 0.2 v not tested i 2 c input/output: sda (referenced to scl; open drain output) low-level output voltage v ol 0.4 v i ol =3ma low-level output voltage v ol 0.6 v i ol = max output fall time from min ( v ih ) to max ( v il ) t of 20 + 0.1 c b /pf 250 ns 10 pf c b 400 pf analog-to-digital converters (6 bit) y, u, v input leakage current C 100 100 na y, u, v input capitance 7 pf not tested input clamping error C 1 1 lsb settled state input clamping current | i clp |15 40 70 50 90 150 m a m a m a deviation < 1 lsb deviation 12lsb deviation > 2 lsb reference voltage difference v refh C v refl 0.98 1.02 v v dda = nom, ( v refh C v refl @ v dda1 /5) digital-to-analog converters (6 bit): current source outputs out1, out2, out3 1) d.c. differential nonlinearity dnle C 0.5 0.5 lsb r ref = 5.1 k w full range output current i o C 1.4 2 C 1.7 3 ma v dda = max, t a = nom, r ref = 5.1 k w, r l = 680 w , after adjustment 3.3 characteristics (contd) parameter symbol limit values unit remark min. max.
sda 9288x semiconductor group 34 03.96 note: the listed characteristics are ensured over the operating range of the integrated circuit unless restricted to nominal operating conditions (all voltages refer to v ss ). the listed characteristics are ensured over the operating range of the integrated circuit. typical characteristics specify mean values expected over the production spread. if not otherwise specified, typical characteristics apply at t a = 25 c and the given supply voltage. output voltage ( v on 1.6 v dda r l / r ref ) v o 0.96 1.18 v v dda = max, t a = nom, r l = 680 w , r ref = 5.1 k w, after adjustment tracking C 3 3 % v dda = max, t a = nom, r ref = 5.1 k w, r l = 680 w contrast increase 30 % v dda = nom, t a = nom, r l = 680 w , r ref = 6.8 k w, contrast bits change from 0000 to 1111 for typical values see chapter 4 supply voltage dependence of dac output current for typical values see chapter 4 temperature dependence of dac output current for typical values see chapter 4 dependence of dac output current on external reference resistor for typical values see chapter 4 1) i 2 c: contrast bits set to zero unless otherwise noted. 3.3 characteristics (contd) parameter symbol limit values unit remark min. max.
sda 9288x semiconductor group 35 03.96 4 diagrams 4.1 output current of da converters nominal values: v dda = 5 v; v ref = 5.1 k w ; t = 25 c measurements after adjustment via bit d7 of i 2 c bus address 0d for each step note: the output currents are controlled in digital way, so inaccuracy of 1 lsb (ca. 2 %) is always possible. output current = f ( v dda ) output current = f ( t a )
sda 9288x semiconductor group 36 03.96 output current = f ( r ref ) current = f (con 0 3)
sda 9288x semiconductor group 37 03.96 4.2 application information 4.2.1 reference voltage generation for adc figure 3 signal input range 1 vpp at y, u, v figure 4 signal input range 2 vpp at y, u, v
sda 9288x semiconductor group 38 03.96 figure 5 signal input range 0.5 vpp at y, u, v
sda 9288x semiconductor group 39 03.96 4.2.2 adjustment of ydel figure 6
sda 9288x semiconductor group 40 03.96 4.2.3 three level interface (3-l) figure 7 high level (h): upper transistor on, lower transistor off medium level (m): both transistors off (interface voltage determined by input stage) low level (l): upper transistor off, lower transistor on
sda 9288x semiconductor group 41 03.96 4.2.4 application board layout proposal figure 8 (top view) figure 9 (bottom view)
sda 9288x semiconductor group 42 03.96 4.2.5 application circuit (r, g, b-mode) figure 10
sda 9288x semiconductor group 43 03.96 4.3 waveforms 4.3.1 timing of adc clamping figure 11 the values are valid if hsidel = 0. to get the maximum values 444 ns for each step of hsidel adjustment must be added (clpfix = 0). with clpfix = 1 there is no influence of the hsidel adjustment to the clamp timing.
sda 9288x semiconductor group 44 03.96 4.3.2 phase relation of sync pulses at frame mode if the phase relation is not correct at the h and v sync inputs, an adjustment via bits vsidel and vspdel is possible. figure 12 signal flow of the horizontal synchronization (insert part) figure 13 allowed phase relation of the horizontal/vertical sync pulses (insert channel) if vsidel(0:4) = 0000
sda 9288x semiconductor group 45 03.96 figure 14 allowed phase relation of the horizontal/vertical sync pulses (parent channel)if vsidel(0:4) = 0000
sda 9288x semiconductor group 46 03.96 5 package outlines gps05697 p-dso-32-2 (plastic dual small outline package) sorts of packing package outlines for tubes, trays etc. are contained in our data book package information dimensions in mm smd = surface mounted device

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